Demo 4 bits full adder and 4 bits multiplier by Verilog

◎ 4 bits full adder

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method_1: step by step module add_4_v ( input [3:0] a, input [3:0] b, input cin, output [3:0] s, output co ); wire [2:0] carry; function fa_s(input a, input b, input cin); fa_s = a ^ b ^ cin; endfunction function fa_co(input a, input b, input cin); fa_co = a & ci | a & b | b & cin; endfunction assign s[0] = fa_s (a[0], b[0], cin); assign carry[0] = fa_co(a[0], b[0], cin); assign s[1] = fa_s (a[1], b[1], carry[0]); assign carry[1] = fa_co(a[1], b[1], carry[0]); assign s[2] = fa_s (a[2], b[2], carry[1]); assign carry[2] = fa_co(a[2], b[2], carry[1]); assign s[3] = fa_s (a[3], b[3], carry[2]); assign co = fa_co(a[3], b[3], carry[2]); endmodule

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method_2: using Mega-function "lpm_add_sub" module add_4_v ( input [3:0] a, input [3:0] b, input cin, output [3:0] s, output co ); lpm_add_sub # (.lpm_width(4)) u0 ( .dataa(a); .datab(b); .result(s); .cout(co); ); endmodule

◎ 4 bits multiplier

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module m(a, b, y); input [3:0] a, b; output [7:0] s; wire [3:0] to, t1, t2, t3; assign to = (b[0]==1)? a : 4'h0; assign t1 = (b[1]==1)? a : 4'h0; assign t2 = (b[2]==1)? a : 4'h0; assign t3 = (b[3]==1)? a : 4'h0; assign s = t0+(t1<<1)+(t2<<2)+(t3<<3); endmodule